Please note, the answers are just for your references.
-Usually driving a small wire with large currents (this happens usually in poer meshes) causes metal fatigue and deformation which furher hampers the ability of the wire to carry electrons effectively. If you look at a wire which has been subjected to EM, the wire looks like it has been melted and re-cooled (deformed). One way to prevent this is to do proper power planning.
Floorplanning is what you do at early stage of the design to get a rough idea about the optimal placemnt of blocks in layout. Power planning is the process of understanding how much power the design requires. Initially you do this by calculating the thickness and number of power rails and straps using an estimated power number for each design and later during post synthesis, you use the numbers you get from design/power compiler to refine your estimates.
The question is too generic. Are they asing about the routing types a given tool uses or routing methods. For routing methods I can think of global routing and detail routing. In global, you roughly place the wires like a flyby wire. In detail routing the tool pushes these wires into the channels. In a typical layout you do both of these.
Is a series of small rectangular boxes/mesh you create over your entire layout to help you place cells.
Two most commonly known grids are –> Manufacturing grid & Routing grid
Manuf. grid - This is minimum dimension of the shape that be successfully fabricated in a particular foundry for a particular technology node.
Routing grid - Normally used by P&R tools , this will be multiple for manuf. grid
Core is the area in chip used for placing all your design excluding the chip IOs. There are a lot of factors that effects w/h such as whether the chip is pad limited or pin limited. Timing or whether you are using a lot of hard macro IPs and memories or if your design is all gates. Also location of chip IOs. For example if your core only talks to the top of the chip then you may want to put all the core pins on top of the core and make w/h to be say 2-1 or 4-1 (long rectangular shape).
Effective utilization refers to ration of placed cells/wire to total area of core used. Chip utilization is the ratio of placed gates/IOs to total area of the chip.
When a signal gets to two different point in the design, is known as latency. For example clock latency is the differnce in time for a clock to arrive at two different flops. Data latency is the time difference between arrival of a data at two different points. IO latency, cell latency and so on….