# Load in netlist read_verilog ... # set some variables for help with constraints debug set sdc_save_source_file_information true set timing_report_unconstrained_paths true # Load in Functional constraints source ./constraints/for_pt/create_clocks.sdc source ./constraints/for_pt/set_false_path.sdc source ./constraints/for_pt/set_disable_timing.sdc source ./constraints/for_pt/set_ideal_network.sdc source ./constraints/for_pt/efuse_constraints.sdc ... # Source core warecw000541 constraints source ./coreware_1/coreware_1.tcl source ./coreware_2/coreware_2.tcl source ./coreware_3/coreware_3.tcl # Define asychronous clock groups source ./constraints/set_clock_groups.sdc # update timing update_timing # Dump reports # report clocks report_clock -nos > clocks.rpt report_clock -nos -groups > clock_groups.rpt # apply zero wire model on design set_wire_load_model -name lsi40_rc_wlm_0.0 -library lsi40_rc_wlm ssdc # Set operating condition set_operating_conditions -analysis_type single -library tsmc_cln40g_schxd_slow_125c_0p81v slow_125_0.81 # update_timing set timing_update_status_level high update_timing > update_timing.log # check timing check_timing -verbose > check_timing.rpt check_timing -verbose -override_defaults no_clock > check_timing_no_clock.rpt # report disable timing arcs report_disable_timing -nos > report_disable_timing.rpt # report analysis coverage statistics report_analysis_coverage -nos -status_details untested -check_type setup -exclude_untested constant_disabled > report_analysis_coverage.rpt # report_design report_design -nos > report_design.rpt # report constraints report_constraints -nos -all > report_constraints.rpt report_constraints -nos -all -verbose > report_constraints_verbose.rpt # timing file for slackPlot report_timing -path full -nosplit -max_paths 10000000 -significant_digits 4 > slack_ends.rpt # save session save_session -replace start.session #quit