做Top STA或Power分析的时候，需要用到Top的Verilog Netlist，但是在DFT的时候没有把所有的模块都uniquify， ICC在做优化的时候会在模块上面加port/pin，所以在Top读网表的时候会模块定义会有冲突。写了个脚本，给各个模块加了个前缀，解决了这个问题。
#! /tools/cfr/bin/python ################################################################ ## ## Used for add module prefix in netlist ## written by donghua.gu@lsi.com ## Thu Dec 22 22:58:45 CST 2011 ## ################################################################ import re import os import sys import sets from optparse import OptionParser def get_all_module_names(lines): patt = """^\s*module\s+([^ ]*)""" module_names = [] for line in lines: if not line: continue module_name = re.findall(patt, line) if module_name: module_name = "".join(module_name) module_names.append(module_name) return module_names def prefix_module_names(lines, module_names, prefix, fixed_module_names): new_lines = [] module_name_set = sets.Set(module_names) patt_instance = """^([A-Za-z0-9_]+)\s+([A-Za-z0-9_]+)\s+\(""" patt_module = """^module\s([^\s]*)\s\(""" for line in lines: if not line.strip(): new_lines.append(line + "\n") continue line = line.strip() + "\n" new_line = line module_instance_pairs = re.findall(patt_instance, line) if module_instance_pairs: module_name = module_instance_pairs[0][0] if module_name in fixed_module_names: pass elif module_name in module_name_set: #print line new_line = prefix + line.strip() + "\n"; module_name = re.findall(patt_module, line) if module_name: module_name = "".join(module_name) if module_name in fixed_module_names: pass else: new_line = "module " + prefix + line[len("module "):].strip() + "\n"; new_lines.append(new_line) return new_lines if __name__=="__main__": usage = "usage: %prog [options] netlist ...\n" usage +="\nSave prefixed netlist to file netlist[p]" parser = OptionParser(usage=usage) #parser.add_option("-o", dest="output_file", # help="file name for modified verilog netlist", metavar="OUTPUT") parser.add_option("-p", "--prefix", dest="prefix", help="prefix for module names, default pre", metavar="PREFIX", default="pre") parser.add_option("-f", "--fixed", dest="fixed", help="fixed module names", metavar="FIXED", default="") (options, args) = parser.parse_args() verilog_files = args prefix = options.prefix fixed = options.fixed.split() #out_file = options.out_file if len(verilog_files) > 1: prefixs = [prefix+"_"+str(i) for i in range(len(verilog_files))] else: prefixs = [ prefix ] for i in range(len(verilog_files)): mprefix = prefixs[i] + "_" v_file = verilog_files[i] print "Proecess %s" % v_file lines = open(v_file, 'r').readlines() lines = [line.strip() for line in lines] module_names = get_all_module_names(lines) new_lines = prefix_module_names(lines, module_names, mprefix, fixed) v_new = "".join(new_lines) new_name = v_file + "p" if os.path.exists(new_name): cmd = "mv %s %s" % (new_name, new_name + ".bk") os.system(cmd) open(new_name, 'w').write(v_new) print " Save %s" % new_name #break
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