目录
ASIC Backend Design
Flow Scripts
VLSI Basic Concept
Models
EDA Tools
IC Design Interview Questoins
VIM Setting
More VLSI
Scripts Utility
ASIC Backend Design
Flow Scripts
Synopsys Implementation Tool Guide
IC Compilier (ICC)
PrimeTime
Design Compiler(DC)
RedHawk
StarRC
calibre
VLSI Basic Concept
Unate
Verilog
FITS Failures in Time
Models
WLM - Wire load Model
Extracted Timing Models (ETM)
AOCV
EDA Tools
SpyGlass
IC Design Interview Questoins
IC Design Interview Question
VIM Setting
VIM Setting For ICC
More VLSI
For more VLSI information, please visit
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Scripts Utility
Prefix Verilog Modules
Create .lib File From Verilog
Get block size by Batch