Python 俱乐部

====== ASIC Backend Design ======

===== Flow Scripts =====
  * [[vlsi:tools:synopsys]]
  * [[vlsi:icc:start]]
  * [[vlsi:pt:start]]
  * [[vlsi:dc:start]]
  * [[vlsi:redhawk:start]]

  * [[vlsi:star-rc:start]]
  * [[vlsi:calibre:start]]
===== VLSI Basic Concept =====

  * [[vlsi:basic:unate]]
  * [[vlsi:verilog:start]]
  * [[vlsi:basic:fail]]
===== Models =====
  * [[vlsi:models:wire-load-model]]
  * [[vlsi:models:etm]]
  * [[vlso:models:aocv]]

===== EDA Tools =====
  * [[vlsi:spyglass:start]]


===== IC Design Interview Questoins =====
  * [[vlsi:interview]]

===== VIM Setting =====
  * [[vlsi:linux:vim:icc]]

===== More VLSI =====
  * For more VLSI information, please visit http://www.truevue.org/vlsi

===== Scripts  Utility=====
  * [[vlsi:scripts:prefix-verilog-module]]
  * [[vlsi:scripts:create-lib-from-verilog]]


  * [[vlsi:scripts:get-block-size]]
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