跳至内容
Python 俱乐部
用户工具
登录
站点工具
搜索
工具
显示页面
修订记录
反向链接
最近更改
媒体管理器
网站地图
登录
>
最近更改
媒体管理器
网站地图
您的足迹:
vlsi:tools:synopsys
====== Synopsys Implementation Tool Guide ====== * Design Compiler – Logic synthesis * [[vlsi/tools/synopsys/design-compiler-topographical|Design Compiler Topographical -- DCT(new feature)]] * Physical Compiler – Physical synthesis * JupiterXT – Floorplanning * Astro – Place and Route for designs down to 65nm design rules * IC Compiler – Next generation Place & Route * Power Compiler – Power optimizations for synthesis * PrimePower – Power analysis * PrimeRail – IR Drop and EM analysis * DFT Compiler – Scan synthesis * TetraMAX – Scan compression * PrimeTime – Signoff timing analysis * PrimeTime-SI – Signoff timing analysis with signal integrity effects * Astro-Rail – Signoff reliability analysis * Hercules – Physical verification * Star-RCXT – Parasitic extraction * HSPICE – Circuit simulation * NanoSim – Mixed signal circuit simulation
vlsi/tools/synopsys.txt
· 最后更改: 2010/06/02 01:18 (外部编辑)
页面工具
显示页面
修订记录
反向链接
回到顶部