用PT产生ETM model是后端Design工程师的最常见任务，如果你做Top的话，那更是家常便饭了。

下面的TCL代码就是PT产生ETM的脚本，以及常用设置。

set extract_model_data_transition_limit 0.75
set extract_model_clock_transition_limit 0.75
set extract_model_capacitance_limit 1.0
set extract_model_num_clock_transition_points 7
set extract_model_num_data_transition_points 7
set extract_model_num_capacitance_points 7
set extract_model_use_conservative_current_slew true
set extract_model_enable_report_delay_calculation true
 
reset_path -hold -from [all_inputs]
reset_path -hold -to [all_outputs]
remove_clock_uncertainty [all_clocks]
 
set_input_transition 0.75 [all_inputs]
 
extract_model -format {lib db} -output ${etm_name} -library_cell

set extract_model_num_clock_transition_points 5
set extract_model_enable_report_delay_calculation true
set extract_model_clock_transition_limit 0.8
set extract_model_data_transition_limit 0.8
set extract_model_num_capacitance_points 5
set extract_model_num_data_transition_points 5
set extract_model_capacitance_limit 0.7
 
set extract_model_with_clock_latency_arcs false
set_propagated_clock [all_clocks]
reset_path -hold -from [all_inputs]
reset_path -hold -to [all_outputs]
remove_clock_uncertainty [all_clocks]
set_input_transition 0.75 [all_inputs]
 
 
if { ($corner == "rcmin") ||($corner == "rcmax")  } {
  extract_model -format {lib db} -output ${rpt_dir}/${topLevel}_clock_${asic_delay_case}_rc -library_cell
  remove_propagated_clock [all_clocks]
  extract_model -format {lib db} -output ${rpt_dir}/${topLevel}_ideal_${asic_delay_case}_rc -library_cell
  merge_model -lib_files "${rpt_dir}/${topLevel}_clock_${asic_delay_case}_rc.lib  ${rpt_dir}/${topLevel}_ideal_${asic_delay_case}_rc.lib" -mode_names {clk_propagated clkideal} -output ${rpt_dir}/topLevel_${asic_delay_case}_rc -format {db lib} -tolerance 0.001
 
} else {
  extract_model -format {lib db} -output ${rpt_dir}/${topLevel}_clock_${asic_delay_case} -library_cell
  remove_propagated_clock [all_clocks]
  extract_model -format {lib db} -output ${rpt_dir}/${topLevel}_ideal_${asic_delay_case} -library_cell
  merge_model -lib_files "${rpt_dir}/${topLevel}_clock_${asic_delay_case}.lib  ${rpt_dir}/${topLevel}_ideal_${asic_delay_case}.lib" -mode_names {clk_propagated clk_ideal} -output ${rpt_dir}/topLevel_${asic_delay_case} -format {db lib} -tolerance 0.001
}