Topographical technology enables you to accurately predict post-layout timing, area, and power during RTL synthesis without the need for wireload model-based timing approximations.

It uses Synopsys' placement and optimization technologies to drive accurate timing prediction within synthesis, ensuring better correlation to the final physical design.

This new technology is built in as part of the DC Ultra feature set and is available only by using the compile_ultra command in topographical mode.

Design Compiler topographical technology is shared with IC Compiler.