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vlsi:tools:synopsys
Synopsys Implementation Tool Guide
- Design Compiler – Logic synthesis
- Physical Compiler – Physical synthesis
- JupiterXT – Floorplanning
- Astro – Place and Route for designs down to 65nm design rules
- IC Compiler – Next generation Place & Route
- Power Compiler – Power optimizations for synthesis
- PrimePower – Power analysis
- PrimeRail – IR Drop and EM analysis
- DFT Compiler – Scan synthesis
- TetraMAX – Scan compression
- PrimeTime – Signoff timing analysis
- PrimeTime-SI – Signoff timing analysis with signal integrity effects
- Astro-Rail – Signoff reliability analysis
- Hercules – Physical verification
- Star-RCXT – Parasitic extraction
- HSPICE – Circuit simulation
- NanoSim – Mixed signal circuit simulation
vlsi/tools/synopsys.txt · 最后更改: 2010/06/02 01:18 (外部编辑)
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